Tutorial: Embedded Digital Signal Processing for Radar Applications
Presented by:
David Martinez
MIT Lincoln Laboratory, USA
Robert Bond
MIT Lincoln Laboratory, USA
Dr. Michael Vai
MIT Lincoln Laboratory, USA
Course Description:
In the last ten years, there has been significant emphasis on advancing sensor systems with active electronically scanned antennas (AESAs). The recent advances in computing technologies make it affordable to exploit the flexibility of AESAs using very high performance embedded computers for signal and image processing. This tutorial presents an overview of applications demanding real-time embedded computing, an introduction to hardware and software implementation techniques, and recent advances in hardware and software standards to achieve rapid technology insertion, and a look into observed embedded computing trends.
Network-centric warfare implies leveraging information from multiple assets in-theater. However, communicating sensor data without significant processing on board the sensor platform would completely clog the available and future communication bandwidth. In the next ten to twenty years, AESA-based sensors will consist of 100 to 1000 sensor channels, with data rates exceeding hundreds of billion bytes per second (driven by analog-to-digital converter sampling rates). Therefore, on-board computation will be necessary to reduce data rates and to transform signal and image data into information. This information from ground, air, and space assets will then be routed across the theater and globally to permit extracting the requisite knowledge needed by our warfighters. The tutorial focuses on the sensor real-time computation to transform data into information demanding computations reaching and, in some cases, exceeding a trillion operations per second.
The tutorial will start by reviewing example applications centered on AESA architectures. These applications will highlight typical computation, communication, and memory requirements, constrained to implementations with stressing low size, weight, and power goals. After setting the application domain and on-board signal and image processing complexity drivers, implementation options are reviewed. The options range from application-specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), digital signal processors (DSPs), and general purpose processors. The tutorial concludes with an introduction to embedded software practices and techniques. Particular emphasis is put on emerging software middleware standards and open system architectures for real-time embedded systems. The tutorial will also cover the emerging challenges and approaches for adapting sensors to operate in a network-centric context. Examples of service-oriented architectures and technologies for networked intelligence, surveillance, and reconnaissance applications will be presented.
This tutorial is designed for system designers, algorithm developers, hardware and software designers, and program managers interested in an overview and introduction to real-time embedded computing with emphasis on AESA-based sensors. The tutorial content will also address emerging trends in hardware, software, and rapid prototyping techniques. The tutorial draws from the authors’ over fifty years of combined experience in these areas.
The tutorial will be based on the recently published book title: “High Performance Embedded Computing, A Systems Perspective”, by David R. Martinez, Robert A. Bond, and M. Michael Vai, CRC, 2008.
Instructor Biographies:
David R. Martinez
Email: dmartinez@ll.mit.eduMr. David R. Martinez is Head of the ISR Systems and Technology Division at MIT Lincoln Laboratory. He received his Bachelor’s degree from New Mexico State University in 1976, and his M.S. degree from MIT, and the E.E. degree jointly from MIT and the Woods Hole Oceanographic Institution in 1979. He completed an M.B.A. from the Southern Methodist University in 1986. He has attended the Program for Senior Executives in National and International Security at the John F. Kennedy School of Government, Harvard University. He was elected IEEE Fellow in 2003.
Since 2004, Mr. Martinez has led the ISR Systems and Technology Division. In this capacity, he oversees over 300 people and has direct line management responsibility for the Division’s programs in the development of advanced techniques and prototypes for surface surveillance, laser systems, active and passive adaptive array processing, integrated sensing and decision support, undersea warfare, and embedded hardware and software computing.
He joined MIT Lincoln Laboratory in 1988 and was responsible for the development of a large prototype space-time adaptive signal processor. Prior to joining MIT Lincoln Laboratory, he was Principal Research Engineer at ARCO Oil and Gas Company responsible for a multidisciplinary company project to demonstrate the viability of real-time adaptive signal processing techniques. He received the ARCO special achievement award for the planning and execution of the 1986 Cuyama Project, which provided a superior and cost-effective approach to 3-D seismic surveys. He holds three U.S. patents.
From 1997 to 1999, he was the founder and chairman of a national workshop on high performance embedded computing. He has also served as keynote speaker at multiple national level workshops and symposia including the tenth High Performance Embedded Computing workshop, the Real-Time Systems Symposium, and the second International workshop on Compiler and Architecture Support for Embedded Systems. He was appointed to serve in the Army Science Board from 1999 to 2004. From 1994 to 1998, he was Associate Editor to the IEEE Signal Processing magazine.
Robert A. Bond
Email: rbond@ll.mit.eduRobert Bond is leader of the Lincoln Laboratory Embedded Digital Systems group. He earned a B.S. degree (honors) in physics from Queen's University, Ontario, Canada in 1978. In his career, he has focused on the research and development of high-performance embedded processors, advanced signal processing technology, and embedded middleware architectures. Prior to coming to Lincoln Laboratory, Mr. Bond worked at CAE Ltd. on radar, navigation, and Kalman filter applications for flight simulators, and then at Sperry where he developed simulation systems for a Naval command and control application. He joined Lincoln Laboratory in 1987. In his first assignment, he was responsible for the development of the Mountaintop RSTER radar software architecture and was coordinator for the radar system integration. In the early 1990s, he was involved in seminal studies to evaluate the use of massively parallel processors (MPP) for real-time signal and image processing. Later, he managed the development of a 200 billion operations-per-second airborne processor, consisting of a 1000-processor MPP for performing radar space-time adaptive processing and a custom processor for performing high-throughput radar signal processing. In 2001, he led a team in the development of the Parallel Vector Library, a novel middleware technology for the portable and scalable development of high-performance parallel signal processors. In 2003 he was one of two researchers to receive the Lincoln Laboratory Technical Excellence Award for his “technical vision and leadership in the application of high-performance embedded processing architectures to real-time digital signal processing systems.”
M. Michael Vai
Email: mvai@ll.mit.eduDr. M. Michael Vai has worked in the area of high performance embedded computing for over 20 years. Dr. Vai has worked and published extensively in very large scale integration (VLSI), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA), design methodology, and embedded digital systems. He has published more than 60 technical papers and a textbook (VLSI Design, CRC Press, 2001). He is also the co-editor and contributing author of a reference handbook (High Performance Embedded Computing Handbook, CRC Press, 2008).
Dr. Vai received his B.S. degree from National Taiwan University, Taipei, Taiwan, in 1979, and his M.S. and Ph.D. degrees from Michigan State University, East Lansing, Michigan, in 1985 and 1987, respectively, all in electrical engineering.
Until July 1999, Dr. Vai was on the faculty of Electrical and Computer Engineering Department, Northeastern University, Boston, Massachusetts. At Northeastern University, he developed and taught the VLSI Design and VLSI Architecture courses. He also established and supervised a VLSI CAD Laboratory. In May 1999, the Electrical and Computer Engineering students presented him with the Outstanding Professor Award. During Dr. Vai’s tenure at Northeastern University, he performed research programs funded by National Science Foundation (NSF), Defense Advanced Research Projects Agency (DARPA), and industry.
Dr. Vai joined MIT Lincoln Laboratory in 1999 and is currently Assistant Leader of the Embedded Digital Systems Group. He has led the development of several notable real-time signal processing systems incorporating high-density VLSI chips and FPGAs. In Spring 2002, Dr. Vai coordinated and taught a VLSI Design course at Lincoln Laboratory. In April 2003, he delivered a lecture “ASIC and FPGA DSP Implementations” in the IEEE lecture series “Current Topics in Digital Signal Processing.”
Dr. Vai’s current research interests include advanced signal processing algorithms and architectures, rapid prototyping methodologies, and anti-tampering techniques. Dr. Vai is a senior member of IEEE.